Boxis R700 Manuel d'utilisateur télécharger pdf (Page 29)

ATI R700 Technology

Program State 2-11

Predicate

R/W No 1 1 A register containing predicate bits. The

bits are set or cleared by ALU instructions

as the result of evaluating some condition;

the bits are subsequently used either to

mask writing an ALU result or as a condi-

tion itself.

An ALU clause computes the predicate bits

in this register. A predicate bit in this regis-

ter can be referred to in a control-flow

instruction to induce conditional branching.

This state only persists for one ALU clause.

Pixel State No No 1 192

(64 x 2

bits)

State bits that reflect each pixel’s active

status as conditional instructions are exe-

cuted. The state can be Active, Inactive-

branch, Inactive-continue, or Inactive-

break.

Valid Mask No No 1 64 A mask indicating which pixels have been

killed by a pixel-kill operation. The mask is

updated when a CF_INST_KILL instruction

is executed.

Active Mask W

(indirect)

No 1 1 bit per

pixel

A mask indicating which pixels are cur-

rently executing and which are not

(1 = execute, 0 = skip). This can be

updated by PRED_SET* ALU instructions

but the updates do not take effect until the

end of the ALU clause.

CF_ALU instructions can update this mask

with the result of the last PRED_SET*

instruction in the clause.

1. An asterisk (*) after a mnemonic string indicates that there are additional characters in the string that define

variants.

Table 2.7 Vertex-Fetch State

State

Access by

R700 S/W

Access by

Host S/W

# per

Thread

Width

(bits) Description

Vertex-Fetch Constants R W 128 84 These describe the buffer format, etc.

Table 2.6 ALU State (Cont.)

State

Access by

R700 S/W

Access by

Host S/W

# per

Thread

Width

(bits) Description

1 2 ... 24 25 26 27 28 29 30 31 32 33 34 ... 391 392

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Boxis R700 Manuel d'utilisateur Page 29

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